At Veridise, Işil is overseeing the strategy, hiring and direction of the company together with the leadership team.

In academia, Işıl Dillig’s main research interests are in program analysis/verification, program synthesis, and automated logical reasoning.

She is dedicated to developing tools and novel techniques aimed at enhancing the security and reliability of software systems. Her research primarily concentrates on automatically proving the absence of certain classes of errors and security vulnerabilities within software. Currently, she has a keen interest in techniques for automatically synthesizing programs from formal or informal specifications, including input-output examples, natural language, or reference implementations.