At Veridise, Işil is overseeing the strategy, hiring and direction of the company together with the leadership team.
In academia, Işıl Dillig’s main research interests are in program analysis/verification, program synthesis, and automated logical reasoning.
She is dedicated to developing tools and novel techniques aimed at enhancing the security and reliability of software systems. Her research primarily concentrates on automatically proving the absence of certain classes of errors and security vulnerabilities within software. Currently, she has a keen interest in techniques for automatically synthesizing programs from formal or informal specifications, including input-output examples, natural language, or reference implementations.
Previous work
Academic work
- SmartPulse: Automated Checking of Temporal Properties in Smart Contracts. Jon Stephens, Kostas Ferles, Ben Mariano, Shuvendu Lahiri, Isil Dillig. In IEEE S&P (Oakland) 2021
- Synthesis Powered Optimization of Smart Contracts vis Data Type Refactoring. Yuepeng Wang, Yanju Chen, Maruth Goyal, James Dong, Yu Feng, Isil Dillig. In OOPSLA’22
- Automated Detection of Under-constrained Circuits in Zero-Knowledge Proofs. Shankara Pailoor, Yanju Chen, Franklin Wang, Clara Rodríguez, Jacob Van Geffen, Jason Morton, Michael Chu, Brian Gu, Yu Feng, Isil Dillig. In PLDI’23
- Semantic Code Refactoring for Abstract Data Types. Shankara Pailoor, Yuepeng Wang, Isil Dillig. In POPL 2024
- Certifying Zero-Knowledge Proofs with Refinement Types. Junrui Liu, Ian Kretz, Hanzhi Liu, Bryan Tan, Jonathan Wang, Yi Sun, Luke Pearson, Anders Miltner, Isil Dillig, Yu Feng. In IEEE Security & Privacy 2024 (Oakland)
Conference presentations
Işil has delivered presentations at conferences and universities. Find all of her presentation here.
Hardening Blockchain Security with Formal Methods
24 min | ETH CC 2021
Computer-Aided Programming Across the Software Stack
57 min | UMass
Program Verification using Abductive Reasoning
42 min | PLMW at POPL’20